Central processing units (CPUs) for personal computers, workstations, servers, graphic processor units (GPU) and memory controllers may use very complex controlled supply voltage generators. The supply voltage generators may be very precise both during an idle condition as well as during load transients. In general, supply voltage generators are input with a voltage of 5V or 12V and generate output voltages ranging from 0.5V to 2V. Mono-phase or multi-phase buck voltage converters, for example, of the type illustrated in FIG. 1, are generally preferred for these applications.
In order to effectively respond to very fast and large load transients (for CPU, up to 100 A in 50 ns) these converters need nonlinear controls that are enabled in presence of load transients and turn on simultaneously all the available phases for sustaining the output voltage.
Specifications for conditions of load transients may be restrictive during load increases as well as during load decreases and it may be advisable not to surpass the design maximum voltage. Independently from the fact that a mono-phase or a multi-phase converter is considered, the feedback network used for controlling the converter modifies the response to load changes. Depending on the fact that either linear or nonlinear techniques are used, as discussed in the U.S. Patent Application Publication No. 2007/0229048 to Zambetti et al., also assigned to the present application's assignee, the disclosure of which is incorporated by reference in its entirety, a converter may respond to a load transient by turning on all the phases (in case of a multi-phase) or only some of them. In any case, the response of the converter may be strongly dependent on the characteristics of the application's feedback network, and of the output filter (windings and capacitances), from the input voltage and from the type of modulation ramp (trailing edge, leading edge, dual edge and eventual nonlinear modulation systems) being used.
Specifications relating to windings, to the switching frequency, to the output capacitance and to the input voltage may be fixed when designing the integrated device. Nevertheless, in order to satisfy all specifications at critical load transients, it is often helpful to increase the output capacitance with a consequent added cost.
Referring to FIG. 1, in order to respond effectively to a load variation, it is helpful to increase the control voltage (COMP) as fast as possible, thus with a large band, in order to always cross the modulation ramp (PWM_RAMP). Therefore, the gain during load transients may be sufficiently large. The effect of a large gain on the control voltage COMP may be useful at relatively low load transient frequency for making effective the response (as shown in FIG. 2 with a dashed line), though this may degrade the response of the system at medium/high load frequencies causing an overshoot on the output voltage and making it exit out of specifications imposed to the load, as illustrated in FIG. 3. The figure shows a qualitative example of the output voltage (VOUT), of the current through the winding (IL), of the modulation ramp (PWM_RAMP) and of the control voltage (COMP) at medium/large load frequency (ILOAD) when the gain on the control voltage COMP varies, in a mono-phase system.
At medium/high frequencies, because of the significant time constant of the output filter, the current through the inductor is stable around the mean value of the two current levels (IREL and IAPP) used by the load. In absence of fluctuations between the load frequency and the switching frequency, that could be prevented for example, by suitably nonlinear systems, the output voltage may be driven with a constant duty-cycle.
As it may be inferred from the example shown, in order to keep the correct duty-cycle, the control system shifts its response toward the functioning zone of load reduction (i.e. transition from a high load current to a low load current) when the voltage gain of the block COMP increases, thus generating a delay in the closed loop response equal to TD. By shifting the response, the excess charge in the inductor (ΔQC—REL) is supplied to the output capacitance, thus producing an overshoot of the voltage (ΔVOVER), i.e. an overshoot increases during the load reduction events that could systematically lead to the maximum output voltage being out of the specifications with consequences on the reliability of the device powered by the converter.
This charge may be estimated with the following formula:
      Δ    ⁢                  ⁢          Q      C_REL        =                    V        OUT                    2        ⁢        L              ⁢                  T        D            ·              T        LOAD            and may generate an overshoot equal to:
                              Δ          ⁢                                          ⁢                      V            OUT_REL                          =                                            V              OUT                                      2              ⁢                              L                ·                                  C                  OUT                                                              ⁢                                    T              D                        ·                          T              LOAD                                                                      From the examples of FIGS. 2 and 3, it is evident that a high gain compensation network in presence of transients may be good at low load frequency but could lead the system out of its specifications, as far as overshoot of the output voltage at medium/high load frequency is concerned.
A known technique for reducing the overshoot of the output voltage during load reductions is known as “Body Brake” or “Diode Emulation.” This technique is based on turning on the free-wheeling diode of the low side MOS (and in case of a multi-phase system of all the low-side MOS) for quickly demagnetizing the output inductors by discharging them with a voltage equal to VOUT+VDIODE wherein VDIODE is the voltage of the free-wheeling diode of the low side MOS when turned on as shown in FIGS. 4 and 5. In order to turn on the free-wheeling diode during a load decrease, it is helpful to monitor the output (U.S. Patent Application Publication No. 2007/0229049 to Zafarana et al., also assigned to the present application's assignee) or, indirectly, the signal COMP for revealing when a load decrement is occurring and placing in a high impedance state both the low side as well as the high side MOS.
Advantages and drawbacks of this technique are well illustrated in the reference authored by Don Caron and titled “Using Diode Emulation To Reduce Output Voltage Overshoot During a Transient Load Release,” and herein incorporated by reference in its entirety. More particularly, this document may illustrate the helpfulness of the use of the Diode Emulation technique at medium/high load frequencies. Indeed, because of the overshoot due to the load reduction at medium/high frequencies (around 350 kHz in the example of FIG. 6), the increment of power consumption by the free-wheeling diode and thus by the low side MOS is particularly large, about 20% larger, and could even compromise thermal design of the application. In low cost designs where thermal design of the application is already done at extreme conditions, such an increment of dissipated power may be problematic.